The present invention relates generally to metal-oxide-semiconductor (MOS) field effect devices, and more particularly to an improved, high speed n-channel MOS inverter structure of the type combining an enhancement-mode driver and a depletion-mode load. The invention also concerns a particularly suitable method for fabricating such a device.
The most basic MOS digital logic circuit is the inverter, which performs the logical NOT function. An elementary MOS inverter consists of an active switching device, or driver, in series with a load device. Almost without exception the load device, like the driver, is an MOS transistor. Inverters can be designed using n-channel or p-channel technologies, with a choice of enhancement-mode or depletion-mode devices for both the driver and load transistors. For most integrated circuit designs the choice of drivers is limited to enhancement-type devices for practical reasons--the use of a depletion-mode driver would not permit voltage polarity matching between direct-coupled stages. The combination of a depletion-type load with an enhancement driver requires the least substrate surface area and hence provides the greatest circuit density, a significant attraction in LSI (large scale integration) applications. Where high performance is required, n-channel MOS technologies have largely replaced p-channel varieties because of the latter's lower speed and larger equivalent size.
The push for higher performance and greater circuit density has resulted in the development of several new n-MOS technologies in recent years. These include a silicon gate process called HMOS (for high-performance MOS) that produces scaled-down versions of conventional n-MOS devices; a planar double-diffusion process called DMOS; and VMOS, another double-diffusion process featuring anistropic etching of a V-shaped groove in the silicon chip. All three have been used to provide enhancement/depletion (e/d) type inverters that include a conventional depletion-mode load device with a relatively long, 5 micron channel under the gate, integrated in series with a short channel enhancement mode driver. None of the processes is without its drawbacks, however. For example, HMOS places very great demands on a manufacturer's ability to form extremely fine patterns accurately and reproducibly. The production of VMOS devices requires the use of two relatively high cost processes, epitaxial deposition and anisotropic etching. DMOS, in which the driver's channel is defined by successive diffusions of p-type and n-type impurities through the same mask opening, requires precision diffusion sources and superior process control to achieve narrow channel widths reproducibly. In addition, both HMOS and DMOS share the disadvantage (where maximum packing density is needed) of being planar processes, which require more wafer surface than non-planar processes such as VMOS.
Accordingly, a principal object of the present invention is to provide a new, high performance enhancement/depletion-mode inverter structure adapted for large and very large scale integration.
A related object of this invention is to provide an improved method for fabricating such devices economically and with a minimum of critical processing steps.
Another object of this invention to provide nonplanar e/d-type MOS inverters by a method that does not include anisotropic etching.
A further object is to provide an improved method of forming silicon gate e/d-type inverters having extremely short channel length drivers.